Method for reducing power consumption of CPU, electronic apparatus, and recording medium having power consumption reduction program recorded thereon

ABSTRACT

Method and apparatus for reducing electrical power consumption of an electronic unit provided with a central processing unit (CPU). The CPU is returned to a normal operation state at regular intervals when the CPU has been placed in a sleep state. The CPU outputs a clear signal to a monitoring circuit, and makes reference to an actuation signal for an external device, such as, for example, a motor from a control switch to place the CPU in the sleep state at a time other than a time when reference is made to the clear signal and the input signal. When the CPU has been released from the sleep state, reference to an output of the clear signal and the input signal and an output of only the clear signal are repeated at regular intervals and at a predetermined frequency.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention pertains to a method and apparatus for reducing apower consumption of a central processing unit (CPU) of an electronicunit by switching the CPU between a normal operating state and a sleepstate, and more particularly, to returning the CPU to the normaloperation state at regular intervals when the CPU has been placed intothe sleep state, outputting a predetermined clear signal from the CPU toa monitoring circuit so that the monitoring circuit monitors the stateof the CPU, and making reference to an input signal to the CPU fromelectronic equipment connected to the CPU, and a recording medium havinga power consumption reduction program recorded thereon.

2. Discussion of Background and Relevant Information

In recent years, electronic devices are being increasingly designedinto, for example, vehicles. Certain electrical devices must remainconnected to an electrical power supply (e.g. vehicle battery) even whenthe vehicle is parked. Thus, such electronic devices consume significantamounts of electrical power twenty-four hours a day. As a result, if thevehicle is parked for an extended period of time, the vehicle batterymay be prematurely run down (exhausted). Accordingly, it is desirable toreduce the electrical demands (i.e., energy demand) of the electronicdevices when the vehicle is parked. One way to reduce the electricalrequirements of such an electronic device (unit) is to place theelectronic device into a sleep state when the vehicle is parked.

A microcomputer (e.g., an electronic device containing a CPU) can beused to control and/or operate and/or monitor a plurality of functions.Thus, it is desirable to include a monitoring circuit, such as, forexample, a watch dog time (or the like) in the electronic device, inorder to return the electronic device to its normal operation statewhen, for example, the vehicle is to be started (or runs), or a vehiclemalfunction or unusual event occurs. If the CPU outputs clear signals tothe monitoring circuit at predetermined time intervals, the monitoringcircuit concludes that the CPU is in a normal operation state. On theother hand, if the monitoring circuit does not receive the clear signalwithin the predetermined time interval, the monitoring circuit concludesthat the CPU has “locked up” or some other problem has occurred, and themonitoring circuit outputs a reset signal to the CPU. Upon receipt ofthe reset signal, the CPU is initialized and, hopefully, returns to aninitial operation state.

When the CPU is placed into the sleep state, the CPU must be returned toits normal operation state at predetermined intervals in order to ensurethat the CPU outputs the clear signal for detection by the monitoringcircuit. That is, the microcomputer must be constructed so as to preventthe CPU from going into a runaway state.

When a signal is inputted to the CPU, it is necessary for the CPU toimmediately perform the required task, even when the CPU is placed inthe sleep state. Therefore, it is necessary to determine whether anactuation signal has been inputted to an input port of the CPU. When theCPU is normally placed in the sleep state, the CPU outputs the clearsignal according to a procedure shown in a timing chart of FIG. 5, andthe flowchart of FIG. 6.

As shown in FIG. 5, after the CPU enters the sleep state, it returns tothe normal operation state for a 10 msec period every 30 msec. The CPUoutputs the clear signal and makes reference to the input port thereof.Then, the CPU is placed back into to the sleep state (steps S21-S23 ofFIG. 6). Thus, the CPU is in the sleep mode for a 20 msec time period ofeach 30 msec time period, during which time the electrical consumptionof the electrical device is reduced.

According to a conventional method for reducing electrical powerconsumption of the CPU, it is necessary for the CPU to output the clearsignal to the monitoring circuit and to make reference to the input portthereof. Thus, it is necessary for the CPU to return to the normaloperation state from the sleep state each time the clear signal isoutputted to the monitoring circuit, and to make reference to the inputport thereof. However, the electrical power consumed by the CPU duringthe transition from the sleep state to the normal operation state causesthe battery to become discharged in a short period of time.

An apparatus for reducing the electrical power consumption of a CPU isdisclosed in Japanese Patent Laid-Open Application No. HEI 8-263326.This apparatus has a first abnormality detection circuit that outputs afirst abnormality detection signal to detect an abnormality of the CPUat regular time intervals when the CPU is placed in the sleep state, anda second abnormality detection circuit that outputs a second abnormalitydetection signal to detect an abnormality of the CPU at regular timeintervals when the CPU is in the normal operating state. The time periodrequired to output the second abnormality detection signal is set to beshorter than the time period required to output the first abnormalitydetection signal, in order to reduce the electrical power consumption ofthe CPU in the sleep state.

A disadvantage of this apparatus is that it requires that the twoabnormality detection circuits generate the different period abnormalitydetection signals in the sleep state and the normal state. Thus, theconstruction of the monitoring circuit is complicated and expensive.Further, the interval at which the reference is made to the input portof the CPU is long. Thus, the abnormality detection circuits areincapable of making a fast response to the actuation of the electronicequipment, which makes an operator feel uncomfortable.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide anapparatus and method for reducing the electrical power consumption of aCPU of an electronic device (unit) making reference to an output of aclear signal that is used to detect an abnormality of the CPU and to aninput signal transmitted to the CPU, and a recording medium that has apower consumption reduction program recorded thereon.

In order to achieve the above object, according to a first embodiment ofthe present invention, there is provided a method for reducing theelectrical power consumption (requirements) of a CPU by returning theCPU to a normal operation state at regular time intervals when the CPUis placed in a sleep state, outputting an abnormality detection clearsignal from the CPU to a monitoring circuit, and making reference to aninput signal transmitted from outside the CPU to place the CPU in thesleep state at a time other than a time when reference is made to theclear signal and the input signal. When the CPU has returned to thenormal operation state from the sleep state, reference to an output ofthe clear signal and the input signal and an output of only the clearsignal are repeated at regular intervals and at a predeterminedfrequency.

According to a feature of the present invention, a frequency of anoutput of only the clear signal is set to be more than that of thereference to an output of the clear signal and the input signal.

According to another object of the present invention, there is providedan electronic apparatus that employs a CPU, in which the electricalpower requirements are reduced by returning the CPU to a normaloperation state at regular intervals when the CPU is placed in a sleepstate, outputting an abnormality detection clear signal from the CPU toa monitoring circuit, and making reference to an input signaltransmitted to the CPU to thereby place the CPU in the sleep state at atime other than a time when reference is made to the clear signal andthe input signal.

When the CPU returns to the normal operation state from the sleep state,a signal generation device repeats reference to an output of the clearsignal and the input signal and an output of only the clear signal atregular time intervals and at a predetermined frequency.

Another advantage of the present invention is that a signal generationdevice is constructed to set the output frequency of only the clearsignal to be more than that of the reference to an output of the clearsignal and the input signal.

According to a still further object of the present invention, there isprovided a recording medium (storage device) that stores a powerconsumption reduction program that is executed by a CPU, in which thepower consumption program includes a first task, a second task, and athird task. The first task returns the CPU to a normal operation stateat regular time intervals when the CPU is placed in a sleep state andoutputs an abnormality detection clear signal from the CPU to amonitoring circuit. The second task makes reference to an input signaltransmitted from outside to the CPU to place the CPU in the sleep stateat a time other than a time when reference is made to the clear signaland the input signal after the clear signal is outputted from themonitoring circuit. The third task repeatedly makes reference to anoutput of the clear signal and the input signal and an output of onlythe clear signal at regular intervals and at a predetermined frequency,when the CPU has returned to a normal operation state from the sleepstate.

According to a feature of the invention, the third task is soconstructed as to set the frequency of an output of only the clearsignal to be greater than that of the reference to an output of theclear signal and the input signal.

It is noted that the reference to the output of the clear signal and theinput signal and the output of only the clear signal are repeated atpredetermined intervals and at a predetermined frequency. Therefore, itis possible to make the reference to the output of the clear signal fordetecting an abnormality of the CPU and the input signal transmitted tothe CPU from outside and reduce the time period required for the CPU togo to the normal operation state from the sleep state. Therefore, theamount of electrical power consumed by the electronic device is reduced.

Further the above-described control can be made by altering the programwithout changing the construction of the CPU. Thus, it is possible tominimize the cost for manufacturing the electronic unit.

It is also possible to secure reference to the input signal to the CPU.Thus, it is possible to immediately actuate the CPU.

According to another object, a method is disclosed for reducing anamount of electrical power consumed by an electronic unit. A CPUassociated with the electronic unit is placed into a sleep state upon anoccurrence of a predetermined event, such as, but not limited to, forexample, the parking of a vehicle. The CPU is then periodically returnedto a normal operation state for a predetermined period of time, so thatit can be determined whether the electronic unit is to perform apredetermined task, such as, but not limited to, operating a powerwindow of the vehicle.

According to a feature of the invention, reference is made to an inputsignal transmitted from an external device to the CPU to place the CPUin the sleep state at a time other than a time when reference is made toa clear signal and the input signal, wherein reference is made to anoutput of the clear signal and the input signal, and to an output ofonly the clear signal, are repeated at regular intervals and at apredetermined frequency when the CPU has returned to the normaloperation state from the sleep state. The clear signal is output to, forexample, a monitoring device.

According to an advantage of the invention, the predetermined frequencyof the output of only the clear signal is set to be greater than thepredetermined frequency of the reference to the output of the clearsignal and the input signal.

According to another advantage, a period for reference to the inputsignal is made longer than a period required for the output of the clearsignal. A predetermined ratio is set for a frequency of the reference tothe output of the clear signal and the input signal to a frequency ofthe output of only the clear signal. The predetermined ratio is set tobe greater than 0 and less than 1, such as, but not limited to, forexample, ½.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, features, and advantages of theinvention will be apparent from the following more particulardescription of the preferred embodiment as illustrated in theaccompanying drawings, in which reference characters refer to the sameparts throughout the various views, and wherein:

FIG. 1 illustrates an example of a power consumption reducing circuit ofthe present invention;

FIG. 2 illustrates a timing chart of a processing signal in a low-powermode according to the embodiment of FIG. 1;

FIG. 3 illustrates a flowchart of a main process executed by a centralprocessing unit (CPU) in accordance with the embodiment of FIG. 1;

FIG. 4 illustrates a flowchart of a low-power mode according to theembodiment of FIG. 1;

FIG. 5 illustrates the timing of a processing signal in a conventionallow-power mode; and

FIG. 6 illustrates a flowchart of the conventional low-power mode ofFIG. 5.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A preferred embodiment of the present invention will be described belowwith reference to the drawings.

FIGS. 1 to 4 illustrate an apparatus and method for reducing theelectrical power requirement (consumption) of a CPU, along with arecording medium that stores a power consumption reduction program.

The construction of the preferred embodiment will now be described. FIG.1 illustrates an electronic unit 1 that serves as an electronicapparatus that controls a power window of a vehicle. The electronic unit1 comprises a voltage reducer 2; a CPU 3; a monitoring circuit 4; aclock generator 5; a first relay 7; a second relay 8; a first switchingdevice 10, such as, for example, a transistor; a second switching device11, such as, for example, a transistor; and protectors R1 to R4.

A positive terminal of an electrical power source, such as, for example,a vehicle battery 12 is connected to an input of the voltage reducer 2.In the disclosed embodiment, the vehicle battery 12 is, for example, a12 volt automobile battery, and the voltage reducer 2 is, for example, avoltage regulator that provides a constant 5 volt output voltage.However, it is understood that the electronic unit 1 can be designed tooperate on alternative power sources, and other output voltages, andthat, further, alternative voltage regulators/voltage reducing devices,such as, but not limited to, for example, a zener diode, a constantcurrent diode, resistor that operates as a voltage regulating device,can be employed without departing from the scope and/or spirit of theinvention.

The output of the voltage reducer 2 is supplied to voltage supplyterminals (not labeled) of the CPU 3 and the monitoring circuit 4,respectively. In the disclosed embodiment, a first output port (notlabeled) of the CPU 3 is connected to the base of transistor 10 via theprotector R3, which may be, for example, a protective resistor. Theemitter of transistor 10 is grounded, while the collector of transistor10 is connected to a coil (not labeled) of the relay 7. Similarly, asecond output port (not labeled) of the CPU 3 is connected to the baseof transistor 11 via the protector R4, which may be, for example, aprotective resistor. The emitter of transistor 11 is grounded, while thecollector of transistor 11 is connected to a coil (not labeled) of therelay 8. A motor 9, such as, for example, a power window motor, isconnected accross switching terminals of the relays 7 and 8.

A controlling device 6, such as, for example, a switch, is connected toinput ports 3 a and 3 b of the CPU 3. In the disclosed embodiment, theswitch 6 is, for example, a single pole, double throw (SPDT) switch,that selects whether the vehicle window is to be opened or closed;however, the invention is not limited to this specific construction, andalternative controlling devices may be utilized by the presentinvention. A first terminal b of the switch 6 is connected to the inputport 3 a of the CPU 3 via protector R1, which may be, for example, aprotective resistor, while a second terminal c is connected to the inputport 3 b of the CPU 3 via protector R2, such as, for example, aprotective resistor. The desired window operation (e.g., opening orclosing of the window) is selected by selectively connecting terminal bor c to ground via contact a of the switch 6.

The monitoring circuit 4 is connected to an input port 3 c of the theCPU3 to receive a reset signal RST issued by the monitoring circuit 4.The CPU 3 outputs a clear signal WDCLR to the monitoring circuit 4 atregular intervals, based on pulse signals generated by the clockgeneration circuit 5. If the clear signal is not inputted to themonitoring circuit 4 within a predetermined period of time, it isconcluded that the CPU 3 has entered into a run-away state or a problem(trouble) has occurred, and the reset signal (RST signal) is outputtedfrom the monitoring circuit 4 to the CPU 3. Upon receipt of the resetsignal, the CPU 3 is initialized and returns to an initial operationstate.

It is noted that the predetermined period of time of the clear signal,and the pulse width of the reset signal can be arbitrarily set by, forexample, varying a capacitor and/or resistor of an RC circuit associatedwith the monitoring circuit 4.

When contact a of switch 6 engages terminal b (or terminal c) of theswitch 6, the CPU 3 applies a voltage to the base of transistor 10 (ortransistor 11). As a result, relay 7 (or relay 8) is turned ON to drivethe motor 9 in a first direction (or a second direction), to therebymove the window upward (or downward).

The CPU 3 monitors input ports 3 a, 3 b and 3 c to determine whether anactuation signal of the motor 9 has been inputted to one of the inputports 3 a and 3 b via the switch 6 and whether the reset signal has beeninputted to the input port 3 c by the monitoring circuit 4.

When the CPU 3 is placed into a sleep state, the CPU 3 returns to thenormal operation state at regular (periodic) time intervals to makereference to the output of the clear signal and an input signal. Thereference to the output of the clear signal and the input signal is madearbitrarily at a frequency set by a low-power mode of a software routineof the present invention, to be described below.

As shown by the timing diagram of FIG. 2, after CPU 3 is placed in thesleep state, the CPU 3 returns to the normal operation state for 10 msecduring each 30 msec time period. Immediately after the CPU 3 returns tothe normal operation state, reference is made for the presence of theclear signal and the input signal. Thereafter, the CPU 3 returns to thesleep state for a 20 msec time period. Upon the expiration of 20 msectime period, the CPU returns to the normal operation state for a timeperiod of 2 msec, during which time the CPU 3 outputs the clear signalWDCLR.

After the clear signal is issued, the CPU 3 returns to the sleep statefor the remainder of the 30 msec time period (e.g., for a time period of28 msec). Upon the expiration of the 28 msec time period, the CPU 3returns to the normal operation state for a 2 msec time period. Theabove-described mode is repeated twice. Thereafter, the above-describedmode is switched to a mode in which reference to the output of the clearsignal and the input signal is made within a 10 msec time period, afterwhich, a mode in which only the clear signal is outputted is twiceexecuted.

In the disclosed embodiment, 2 msec is set for the output of the clearsignal, and 8 msec is set for the reference to the input signal.However, it is understood that these time periods, as well as theabove-discussed time periods, may be varied without departing from thespirit and/or scope of the invention. That is, the disclosed timeperiods are not absolute time periods, but are merely examples of timeperiods that may be used to practice the present invention.

The CPU 3 executes a plurality of programs (referred to, hereinafter, asa first program, a second program, and a third program) that are (havebeen) recorded to a recording medium (storage device), such as, but notlimited to, for example, a RAM, a ROM, a CD-ROM (that is read by, forexample, a CD-ROM drive), a floppy disk (that is read by, for example, adisk drive), a DVD (that is read by, for example, a DVD drive), a harddisk, a flash memory, a memory cartridge, and the like. In this regard,it is understood that the programs of the present invention may bestored in (with) any type of storage device that is capable of storinginformation.

In the disclosed invention, the CPU 3 includes a read only memory (ROM)therein (not labelled) that stores the routines to be described below.However, it is understood that an external ROM that is interfaced to theCPU may be substituted in place of the disclosed CPU that contains abuilt-in ROM. Furthermore, random access memory (RAM) that is eitherbuilt into the CPU or is external of the CPU may be used in place of theROM, and/or an interface may be provided that enables connection of, forexample, the CD-ROM drive, the DVD drive, the floppy drive, the harddisk, the flash memory, the memory cartridge, and the like to the CPU.

The CPU 3 of the disclosed embodiment includes a signal generationdevice. However, it is understood that the signal generation device canbe external to the CPU 3 without departing from the spirit and/or scopeof the invention.

The operation will now be described below with reference to FIGS. 3 and4.

FIG. 3 illustrates an example of the main processing routine that isexecuted when the CPU 3 is in the normal operation state. FIG. 4illustrates an example of a low-power mode processing routine that isexecuted by the CPU 3 when it is placed in the sleep state. In thisregard, it is understood that the illustrated flowcharts are justexamples, and that alternative routines (programs) that achievesubstantially the same result may be designed without departing from thescope and/or spirit of the invention.

In this regard, it is noted that all time periods mentioned herein aremerely examples, and the disclosed time periods may be varied withoutdeparting from the scope and/or spirit of the present invention. As longas the CPU 3 is placed in the sleep mode for any period of time, areduction in the amount of electrical power consumed by the electronicunit 1 will be achieved.

With reference to FIG. 3, when the CPU 3 is running in the normaloperation state, processing a normal process (e.g., first task) foropening and closing the vehicle window and the output of the clearsignal are executed at step S1. Thereafter, at step S2, it is determinedwhether the CPU has been placed into the low-power mode, such as occurs,for example, when the vehicle is parked. If the CPU 3 has beeninstructed to enter the sleep mode, step S3 is executed to perform alow-power mode process, to be described below. However, if the CPU 3 hasnot been placed in the sleep mode, processing returns to step S1 toperform the normal process.

After step S3 is executed, processing proceeds to step S4 to determinewhether a change in input has occurred in the processing for thelow-power mode. That is, it is determined whether switch 6 has beenoperated, or whether the reset signal has been inputted to the CPU 3. Ifthe determination is negative, processing returns to step S3 to executethe low-powere routine. If the determination is affirmative, processingreturns to step S1 to execute the normal processing routine.

In the low-power mode, shown in FIG. 4, a determination is made as towhether a certain (e.g., 30 msec) time period has elapsed from when theCPU 3 entered the sleep state (step S11). If the determination isnegative, processing returns to step S11.

If the determination is affirmative, processing proceeds to step S12 tooutput a clear signal. Then, it is determined at step S13 whether apredetermined number of processings (such as, but not limited to, forexample, a first or a fourth processing) for returning the CPU 3 to thenormal operation state has been executed. In this case, it is determinedthat the first processing has been executed because the determination ismade immediately after the CPU 3 goes into the sleep state. Then,reference is made as to whether an actuation signal has been input tothe input ports 3 a to 3 c (step S14). However, if the determination atstep S13 is negative, processing returns to step S11.

After the processing of step S14 is completed, processing returns tostep S1 to determine whether another certain (30 msec) time period haselapsed. If another 30 msec time period has elapsed (e.g., thedetermination is positive), the CPU 3 outputs the clear signal (step12), and determines whether first or fourth processing for returning theCPU 3 to the normal state has been executed (step S13). Since this loopis the second processing time that the CPU 3 has been returned to thenormal operation state, processing returns to step S11 without makingreference to the input signal.

When the program determines that another 30 msec time period has elapsedat S11, the CPU 3 outputs the clear signal (step 12), and, once again,it is determined whether a first or a fourth processing for returningthe CPU 3 to the normal state has been executed (step S13). This time,it is determined that a third return of the CPU 3 to the normal statehas been executed, and thus, processing returns to step S11 withoutmaking reference to the input signal (that is, step S14 is notperformed).

After the 30 msec time period has elapsed for the fourth time and theCPU 3 has output the clear signal (steps S11 and S12), it is determinedat step S13 (for the fourth time) whether a first or a fourth processingfor returning the CPU 3 to the normal operation state. As step S13 isexecuted for the fourth time, the determination is affirmative, andthus, processing proceeds to step S14, to determine whether an actuationsignal has been inputted to the input ports 3 a to 3 c.

As described above, the reference to the output of the clear signal andthe input signal and the output of only the clear signal are repeated atpredetermined intervals and at a predetermined frequency. Therefore, itis possible to easily make reference to the output of the clear signalfor detecting an abnormality of the CPU 3 and the input signaltransmitted to the CPU 3 from outside. It is also possible to reduce (orvary) the time period required for the CPU to go to the normal operationstate from the sleep state. Therefore, the power consumption of theelectronic device unit 1 is significantly reduced.

Since the programs are stored in a recording medium, they can be easilyaltered without having to change (revise) the construction of theelectronic unit 1, and in particular, the CPU 3. Thus, it is possible tominimize (or prevent) increases in the cost of manufacturing theelectronic unit 1 when the programming is modified.

The reason the output of only the clear signal is executed when the CPU3 returns to the normal operation state from the sleep state is becauseattention is paid to the fact that the period of time required to makethe reference to the input signal is longer than the period of timerequired for the output of the clear signal. In the disclosedembodiment, a ratio of a frequency of the reference to an output of theclear signal and the input signal to a frequency of the output of onlythe clear signal is set to be equal to approximately ½. Therefore, thepower consumption can be significantly reduced. As noted above, it isunderstood that ratios other than ½ (e.g., a ratio greater than 0 butless than 1) may be substituted without departing from the scope and/orspirit of the invention.

In addition, as described above, the frequency of the output of only theclear signal is set to be more than that of the reference to the outputof the clear signal and the input signal. Thus, the operation of the CPU3 can always be monitored, which minimizes the possibility ofintereference.

The frequency of the reference to the output of the clear signal and theinput signal and the set time periods can be set according to aspecification required by a system. Preferably, the number of processingtimes required for recognizing the input of the actuation signal is soset as to not make an operator of the switch 6 feel that an inordinatedelay occurs between the time the switch 6 is operated until the timethe motor 9 operates to open (or close) the vehicle window.

According to the present invention, reference to the output of the clearsignal and the input signal and the output of only the clear signal arerepeated at predetermined intervals and at a predetermined frequency.Therefore, it is possible to make the reference to the output of theclear signal for detecting an abnormality of the CPU 3 and the inputsignal transmitted to the CPU 3 from outside minimal, and to reduce thetime period required for the CPU to go to the normal operation state(mode) from the sleep state. Therefore, the power consumption of theelectronic unit 1 can be reduced.

In addition, the frequency of the output of only the clear signal is setto be greater than that of the reference to the output of the clearsignal and the input signal. Thus, the operation of the CPU 3 can alwaysbe monitored, which reduces the risk of interference.

While the invention has been particularly shown and described withreference to the preferred embodiments thereof, it is understood bythose skilled in the art that various alterations in form and/or detailmay be made without departing from the spirit and/or scope of theinvention, as defined by the following claims. Although the inventionhas been described with reference to the particular means, materials andembodiments, it is to be understood that the invention is not limited tothe particulars disclosed herein, but extends to all equivalents withinthe scope of the claims.

The present disclosure relates to subject matter contained in JapaneseApplication No. 2000-379565, filed on Dec. 14, 2000, which is expresslyincorporated herein, by reference, in its entirety.

1. A method for reducing an electrical power consumption of a CPU,comprising: returning the CPU to a normal operation state, from a sleepstate, at regular intervals when the CPU is placed in the sleep state;outputing an abnormality detection clear signal from the CPU to amonitoring circuit; and making reference to an input signal transmittedfrom an external device to the CPU to place the CPU in the sleep stateat a time other than a time when reference is made to the clear signaland the input signal, wherein reference to an output of the clear signaland the input signal, and an output of only the clear signal, arerepeated at regular intervals and at a predetermined frequency when theCPU has returned to the normal operation state from the sleep state. 2.The method of claim 1, wherein the predetermined frequency of the outputof only the clear signal is set to be greater than the predeterminedfrequency of the reference to the output of the clear signal and theinput signal.
 3. An electronic apparatus, comprising: a CPU that isselectively switched between a normal operation state and a sleep statein which an amount of electrical power consumed by said CPU is reduced,said CPU being returned to the normal operation state at regularintervals when said CPU is placed in said sleep state, said CPUperiodically outputting an abnormality detection clear signal to amonitoring circuit and making reference to an input signal transmittedfrom an external device to said CPU that places said CPU into said sleepstate at a time other than when reference is made to said clear signaland said input signal; and a signal generation device that references anoutput of said clear signal and said input signal, and an output of onlysaid clear signal, at regular intervals and at a predetermined frequencywhen said CPU returns to said normal operation state from said sleepstate.
 4. The electronic apparatus of claim 3, wherein said signalgeneration device sets said frequency of said output of only said clearsignal to be greater than said frequency of said reference to saidoutput of said clear signal and said input signal.
 5. A recordingmedium, comprising: a power consumption reduction program executed by aCPU, said power consumption reduction program including: a first taskthat functions to return said CPU to a normal operation state at regulartime intervals when said CPU has been placed into a sleep state, saidfirst task instructing said CPU to output an abnormality detection clearsignal to a monitoring device; a second task that makes reference to aninput signal transmitted from an external device to said CPU to placesaid CPU in said sleep state at a time other than when reference is madeto said clear signal and said input signal, after said clear signal isoutputted from said monitoring device; and a third task that referencesan output of said clear signal and said input signal, and an output ofonly said clear signal, at regular time intervals and at a predeterminedfrequency when said CPU returns to said normal operation state from saidsleep state.
 6. The recording medium of claim 5, wherein said third tasksets said predetermined frequency of an output of only said clear signalto be greater than said predetermined frequency of said reference tosaid output of said clear signal and said input signal.
 7. The recordingmedium of claim 5, wherein the recording medium comprises a storagedevice.
 8. A method for reducing an amount of electrical power consumedby an electronic unit, comprising: placing a CPU associated with theelectronic unit into a sleep state upon an occurrence of a predeterminedevent; periodically returning the CPU to a normal operation state, fromthe sleep, for a predetermined period of time; and determining whetherthe electronic unit is to perform a predetermined task when the CPU isreturned to the normal operation state for the predetermined period oftime, wherein the determining comprises making reference to an inputsignal transmitted from an external device to the CPU to place the CPUin the sleep state at a time other than a time when reference is made toa clear signal and the input signal, wherein reference to an output ofthe clear signal and the input signal, and reference to an output ofonly the clear signal, are repeated at regular intervals and at apredetermined frequency when the CPU has returned to the normaloperation state from the sleep state.
 9. The method of claim 8, furthercomprising periodically outputting the clear signal from the CPU to amonitoring device.
 10. The method of claim 8, further comprising settingthe predetermined frequency of the output of only the clear signal to begreater than the predetermined frequency of the reference to the outputof the clear signal and the input signal.
 11. The method of claim 8,further comprising making a period for reference to the input signallonger than a period required for the output of the clear signal. 12.The method of claim 8, further comprising setting a predetermined ratiofor a frequency of the reference to the output of the clear signal andthe input signal to a frequency of the output of only the clear signal.13. The method of claim 12, wherein the predetermined ratio is greaterthan 0 and less than
 1. 14. The method of claim 12, wherein thepredetermined ratio is ½.